1. Field of the Invention
The present invention relates generally to computer systems. More particularly, the present invention relates to circuitry that forms a communications "bridge" between components in a personal computer system. Still more particularly, the present invention relates to a bridge logic device that implements an improved sequence for transitioning the computer to a low power mode of operation.
2. Background of the Invention
A personal computer system includes a number of components with specialized functions that cooperatively interact to produce the many effects available in modern computer systems. The ability of these various components to exchange data and other signals is vital to the successful operation of a computer system. Most, if not all, personal computers (PC's) include a processor (or CPU), random access memory (RAM) comprising the computer's main or system memory, and a variety of input and output devices such as a keyboard, mouse, trackball, display (or monitor) to name a few. Typically, the CPU controls most of the activities of the computer system. The CPU supervises data flow and is responsible for most of the high-level data manipulation in the computer. The CPU, therefore, is the brains of the computer system and receives signals from the peripheral devices, reads and writes data to memory, processes data, and generates signals controlling the peripheral devices.
As the processing demands of computer operators have become more sophisticated, PC's have been incorporated with additional hardware such as modems, CD ROM drives, digital video disk (DVD) drives, sound cards, video cards, and scanners. The components of the PC listed above, as well as other devices not listed, are generally interconnected by one or more "busses."
A bus is a collection of digital lines generally including address, data, and control signals. A typical bus interconnects two or more devices. The bus provides an efficient way to transfer data or commands from one device on the bus to another device also connected to the bus. To facilitate communication between bus devices, each bus device is given a unique identifier or address. Thus, one device (the "sending" device) can transfer data to another device (the "receiving" device) by placing an address unique to the receiving device on the bus along with the data to be transferred. The sending device asserts various control signals to initiate the data transfer. All of the other bus devices examine the address, but only the device to which the address corresponds will download the data from the bus.
One early bus that still is in use today is the ISA (Industry Standard Architecture) bus. The ISA bus, as the name implies, was a bus standard adopted by computer manufacturers to permit the manufacturers of peripheral devices to design devices that would be compatible with computer systems of most computer companies. The ISA bus includes 16 data lines and 24 address lines and operates at a clock speed of 8 MHz. A number of peripheral components have been developed over the years to operate with the ISA protocol.
Since the introduction of the ISA bus, computer technology has continued to evolve at a relatively rapid pace. New peripheral devices have been developed, and both processor speeds and the size of memory arrays have increased dramatically. In conjunction with these advances, designers have sought to increase the ability of the system bus to transfer more data at a faster speed. One way in which the system bus has been made more effective is to permit data to be exchanged in a computer system without the assistance of the CPU. To implement this design, however, a new bus protocol had to be developed. One such bus that permits peripheral devices to run cycles independently of the CPU as a "master" device is the EISA (Extended Industry Standard Architecture) bus. The EISA bus enables various system components residing on the EISA bus to obtain mastership of the bus and to run cycles on the bus. Another bus that has become increasingly popular is the Peripheral Component Interconnect (PCI) bus. Like the EISA bus, the PCI bus has bus master capabilities. The PCI bus also operates at a clock speed of 33 MHz or faster.
Because of the bus mastering capabilities and other advantages of the PCI (and EISA) bus, many computer manufacturers now implement one or the other of these busses as the main system bus in the computer system. Because of the proliferation of devices that had been developed for the ISA bus, the computer manufacturers also continued to provide an ISA bus as part of the computer system to permit the use of the many peripheral devices that operated under that protocol. To further provide flexibility, some computer manufacturers provide all three busses in the same computer system to permit users to connect peripheral devices of all three protocols to the computer system. Io implement these various busses in the same computer system, special bridge logic circuit has been developed to interface to the various busses.
Thus, the PC generally includes multiple busses, such as PCI bus, an ISA bus, and an EISA bus, as well as other busses such as a Pentium.RTM. bus and a Small Computer Systems Interface (SCSI) bus. Devices connected to a particular bus must comply with a particular protocol for communicating with other devices on the same bus. The protocol varies between the bus standards. For example, the way devices communicate with each after over a PCI bus generally differs from the way devices on an ISA bus communicate.
FIG. 1 shows a representative prior art computer system that includes a CPU coupled to a bridge logic device via a CPU bus. This bridge logic device is sometimes referred to as a "North bridge" for no other reason than it often is depicted at the upper end of a computer system drawing. The North bridge also couples to the main memory array by a memory bus. The North bridge couples the CPU and memory to the peripheral devices in the system through a PCI bus or other expansion bus (such as an EISA bus). Various components that understand PCI protocol may reside on the PCI bus, such as a graphics controller.
If other expansion busses are provided in the computer system, another bridge logic device typically is used to couple the PCI bus to that expansion bus. This bridge logic is sometimes referred to as a "South bridge" reflecting its location vis-a-vis the North bridge in a typical computer system drawing. In FIG. 1, the South bridge couples the PCI bus to an ISA bus. Various ISA-compatible devices are shown coupled to the ISA bus. Exemplary bridge logic also is described in U.S. Pat. No. 5,634,073, assigned to Compaq Computer Corporation.
The application entitled "Computer System With Memory Controller and Bridge Interface Permitting Concurrent Operation," assigned to Compaq Computer Corp. describes a North bridge which includes a number of write request and read data storage queues to facilitate concurrent flow of write requests and data through the bridge. Such a bridge device permits the computer system to operate more efficiently. Cycle information flowing concurrently through the bridge between pairs of busses (for example, from the CPU bus to the memory bus) creates the potential for certain data coherency problems. These coherency problems, in part, are a result of the characteristics of one or more of the busses connected to the bridge.
By way of example, many bus protocols today implement the concept of "retry." Referring still to FIG. 1, if the graphics controller needs to read data from memory, but the memory is busy servicing an access request from the CPU, the North bridge can retry the graphics controller's read request. That is, the North bridge asserts a signal to the graphics controller directing the graphics controller to retry its read request at a later time. Retrying the cycle frees up the PCI bus to perform other transfers rather than waiting for access to memory.
Other reasons exist for retrying a PCI cycle. For example, retrying a PCI read from memory may be needed to avoid a data "coherency" problem. Generally, it is important for a write cycle to run before a read cycle. To solve this problem, the PCI standard requires any write cycles in the North bridge pending to be run on the PCI bus to be executed before permitting a PCI read to run. The North bridge generally includes a CPU-to-PCI write queue in which the CPU stores write cycles to be run on the PCI bus. The North bridge is responsible for running those cycles. If a PCI read is initiated, the North bridge must first run all write cycles pending in its CPU-to-PCI queue before the PCI read can run. The process of running all pending write cycles in the queue is referred to as "flushing" the queue. The North bridge retries the PCI read cycle while it flushes its write queue.
This methodology for overcoming a possible data coherency problem does not work in some situations. Case in point is the ISA bus. The ISA standard generally does not permit an ISA device to be retried. Accordingly, once an ISA device is granted ownership of the ISA bus to run a read cycle to memory for example, the South bridge must also obtain ownership of the PCI bus so that the cycle can go through to memory without delay. Once the South bridge obtains ownership of the PCI bus on behalf of an ISA device, the South bridge will not relinquish ownership until the ISA cycles completes and the data is read from memory. A conflict thus occurs between the PCI rule that a read cycle first requires the North bridge to flush its internal CPU-to-PCI write queue and the inability of the South bridge to relinquish control of the PCI bus to permit the North bridge to flush its queue.
To overcome this problem, the South bridge and North bridge implement a pair of control signals--flush request (FLUSHREQ) and memory acknowledge (MEMACK). Before granting an ISA device ownership of the ISA bus and obtaining ownership of the PCI bus, the South bridge first asserts FLUSHREQ to the North bridge. In response to FLUSHREQ, the North bridge flushes all CPU-to-PCI write requests pending in the CPU-to-PCI write queue. The North bridge also disallows the CPU from posting additional CPU-to-PCI write requests to the queue (referred to as a "no post" condition). After flushing the CPU-to-PCI write queue and placing the CPU into a no post condition disallowing additional write cycles to be posted to the queue, the North bridge asserts MEMACK back to the South bridge. Upon detecting MEMACK active, the South bridge may then proceed with the ISA cycle according to standard convention.
Although this technique solves the problem noted above, another problem may occur. Many computers include various low power modes of operation. These low power modes are particularly important for portable computers that often run off battery power. A portable computer may include an "idle" mode, a "standby" mode, and a "hibernation" mode, for example. In the standby mode, the computer effectively is turned off except for main memory which continues to be refreshed to preserve the memory contents. The computer may transition into the standby mode if the operator presses a particular button or a predetermined period of time has elapsed during which the computer has been inactive (i.e., the operator has pressed no keys and the computer has otherwise done nothing other than refresh memory). Pressing the same button again brings the computer back to its full operational state.
The hibernation mode is similar to the standby mode except the contents of main memory are copied to a file on the hard drive and the computer effectively is turned off. Once the computer transitions back to its full operational mode (by pressing a particular button), the main memory is restored from the hard drive file and the computer can then continue normal operation. The hibernation mode generally requires less battery power than the standby mode because the battery is not used to refresh memory during hibernation.
The computer's CPU usually is tasked with the primary responsibility of transitioning the computer into the desired low power mode. These responsibilities generally include disabling various functions in the computer and then indicating to an I/O controller that the CPU has completed the task of placing the computer into the low power mode. Some of the steps taken by the CPU to transition the computer to the low power mode of operation involves the CPU running one or more cycles on the PCI bus. For example, the CPU will run a PCI cycle to indicate to the I/O controller that the computer is prepared for the low power mode. The I/O controller will respond to this indication from the CPU by turning off power to a predetermined set of devices in the computer such as the hard drive and floppy drive.
Another step performed during the transition to the low power mode is disabling arbitration of the PCI bus. A PCI arbiter, which is a logic unit that may be included in the South bridge, determines which device connected to the PCI bus will be given control of the bus for each transaction on the bus. Disabling PCI arbitration precludes any device from running a PCI cycle. The only exception is the CPU which is permitted continued access to the PCI bus. Continued PCI access for the CPU is necessary to place the computer in the low power mode.
The problem noted above that the FLUSHREQ/MEMACK protocol could create is if the South bridge asserts FLUSHREQ and the CPU then needs to run a cycle on the PCI bus with FLUSHREQ active. Because the North bridge responds to FLUSHREQ by keeping the CPU from initiating new cycles to the PCI bus, the CPU will not be able to run a PCI cycle. Thus the CPU will not be able to signal the I/O controller to turn power off. Further, because PCI arbitration may be disabled by the CPU as it attempts to transition the computer to the low power mode, the ISA device that caused the South bridge to assert FLUSHREQ will not be permitted access to the PCI bus to complete the cycle it desires. At this point the computer may "lock up." The CPU cannot access the PCI bus (because FLUSHREQ is asserted) to complete the transition to the low power mode and the ISA device which caused the FLUSHREQ cannot access the PCI bus (because PCI arbitration is disabled). Both activities are at a standstill and are unable to complete.
It thus would be desirable to complete the transition to the low power mode of operation without the computer locking up because of an outstanding FLUSHREQ signal. A computer system is needed that solves this problem.